A charge coupled device among semiconductor integrated circuits (hereinafter referred to as "CCD"), typically includes a charge detection circuit which is called as a floating diffusion amplifier which converts a charge-voltage.
FIG. 6(a) shows a cross-sectional structure of a floating diffusion type amplifier used as an output circuit of a CCD. In FIG. 6(a), a CCD final gate electrode 2 and a voltage barrier production gate electrode 3 are arranged opposite a first conductivity type semiconductor substrate. One of the driving clock signals for the charge transfer signal .PHI.H is applied to the gate electrode 2 and a DC voltage VG.sub.0 is applied to the gate electrode 3. At a region adjacent to the gate electrode 3, a MOS transistor comprising a gate electrode 4 and second conductivity type high impurity concentration regions 5 and 6 is produced. To the gate electrode 4 of this MOS transistor, a reset clock signal .PHI.B is applied. When the reset clock .PHI..sub.R signal is high, the MOS transistor is turned on. Further, a reset power supply VR is connected to the impurity region 6.
The impurity region 5 is called a floating diffusion region, and is connected to a gate of a source follower transistor Tr.sub.0 for outputting the signal which is produced on the semiconductor substrate 1. A source follower power supply V.sub.0 is applied to the drain of the transistor Tr.sub.0. Further, the source of the transistor Tr.sub.0 is grounded through a load resistance R.sub.0 and an output signal D.sub.0 is output from the node at which the source and the load resistance R.sub.0 are connected.
The device will operate as follows.
FIGS. 6(b) to 6(d) show the potentials of the respective portions of FIG. 6(a) at times corresponding to t.sub.1 to t.sub.3, respectively, of the clock timing chart of FIG. 7.
First of all, at time t.sub.1 of FIG. 7, the driving clock signal .PHI.H is high, and a potential well is produced at below the gate electrode 2 as shown in FIG. 6(b), thereby storing signal charges Q. At the same time, the clock reset signal .PHI.R is high, and the MOS transistor including the gate electrode 4 and the impurity regions 5 and 6 is turned on, and the voltage at of the impurity region 5 and the gate of the transistor Tr.sub.0 are reset to the reset power supply voltage VR.
Next, at time T.sub.2 of FIG. 7, the reset clock signal .PHI.R becomes low, and the MOS transistor including the gate electrode 4 and the impurity region 5 is turned off (refer to FIG. 6(c)). When the reset clock signal .PHI.R changes to low from high, the voltage of the impurity region 5 is lowered due to the capacitive coupling of the gate electrode 4 to the impurity region 5. When the reset clock signal .PHI.R is low, the node connected to the impurity region 5 floats.
Next, at time T.sub.3 of FIG. 7, when the driving clock signal .PHI.H becomes low, the signal changes Q stored at the potential well below the gate electrode 2 are read out to the impurity region 5 (refer to FIG. 6(d)), and the voltage of the node of the impurity region 5 changes. This voltage change is output through the source follower circuit. The amplitude of the output signal .DELTA.V is represented by the following formula when the capacitance of the floating diffusion node is C.sub.FD and the gain of the source follower is G, ##EQU1## The gain of the source follower is usually about 0.7 to 0.9 without variations. In order to increase .DELTA.V for a particular charge quantity Q, it is necessary to lower the capacitance C.sub.FD. As .DELTA.V is made larger for the same charge quantity Q, the charge-voltage conversion gain is larger, which is advantageous for the signal-to-noise ratio.
On the other hand, the maximum charge quantity which can be detected by the charge detection circuit is the charge quantity which provides a voltage change which does not exceed the channel potential below the gate electrode 3 even when the signal charges are stored at the impurity region 5. Thus the capacitance C.sub.FD determines the maximum quantity of charges which can be detected. When the C.sub.FD is reduced to increase the charge-voltage conversion gain, the voltage change of the floating diffusion portion is increased but the maximum charge quantity detected is reduced.
FIG. 8 shows the relation between the quantity Q of signal charges which are electrically and optically generated by the CCD and the amplitude of the output signal of the source follower transistor, .DELTA.V. As shown in the figure, the relation between the Q and .DELTA.V is linear up to the saturation level, D.sub.0max, of the output which is determined by the design of CCD and the circuit of the source follower transistor. When the signal exceeds the saturation level, the output .DELTA.V is saturated as a function of the input Q, i.e., shifted from linear characteristics. When the capacitance C.sub.FD is decreased and the amplitude .DELTA.V of the output as a function of the charge quantity Q of the input is increased from a to b as shown in the figure, thereby to increase the charge-voltage conversion gain, the maximum charge quantity is reduced from Qa.sub.max to Qb.sub.max. Small signal charge q.sub.s, is superimposed on the background and cannot be detected.